1. Field of the Invention
The present invention relates to an address latch circuit of a memory device, and more particularly to such an address latch circuit wherein a latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition, thereby making it possible to reduce power consumption caused during the level transition of the address signal.
2. Description of the Related Art
In general, memory devices employing synchronous dynamic random access memories (DRAMs) require a very small amount of current consumption, and the amount of current consumption is one of the main factors to be extremely sensitively handled in battery-equipped devices such as notebook computers.
DRAMs must also have a latch circuit that latches an external address signal for a read/write operation of a specific memory cell or an internal address signal for a refresh operation of the memory cell for a predetermined period of time and then transfers the latched external or internal address signal to an associated bank.
FIG. 1 is a circuit diagram showing the configuration of an address latch circuit of a conventional memory device.
As shown in FIG. 1, the address latch circuit comprises a first transfer circuit 10 for transferring an external address signal eat<k> in response to an external address control signal extaxp, a second transfer circuit 15 for transferring an internal address signal iat<k> in response to an internal address control signal intaxp, a latch 20 for latching the external address signal eat<k> or internal address signal iat<k> transferred from the first or second transfer circuit 10 or 15, and an output driver 30 for amplifying and outputting the external address signal eat<k> or internal address signal iat<k> latched by the latch 20.
The external address control signal extaxp is able to drive large fan-out and load and is generated by generating an external address before control signal extaxp_before before the external address control signal extaxp is generated, namely, earlier by a delay time of a first delay 11 than the external address control signal extaxp, and passing the generated external address before control signal extaxp_before through a drive device, such as the first delay 11. Similarly, the internal address control signal intaxp is able to drive large fan-out and load and is generated by generating an internal address before control signal intaxp_before before the internal address control signal intaxp is generated, namely, earlier by a delay time of a second delay 16 than the internal address control signal intaxp, and passing the generated internal address before control signal intaxp_before through a drive device, such as the second delay 16.
The latch 20 includes a first inverter INV1 for inverting the external address signal eat<k> or internal address signal iat<k> transferred from the first or second transfer circuit 10 or 15, and a second inverter INV2 for inverting an output signal from the first inverter INV1 and applying the inverted signal as an input signal to the first inverter INV1 to latch the external address signal eat<k> or internal address signal iat<k>.
Accordingly, if the external address signal eat<k> is externally inputted, the external address control signal extaxp is generated to turn on a first transfer transistor 12 of the first transfer circuit 10, so as to transfer the external address signal eat<k>. Similarly, if the internal address signal iat<k> is internally inputted from an address generator (not shown) for a refresh operation, the internal address control signal intaxp is generated to turn on a second transfer transistor 14 of the second transfer circuit 15, so as to transfer the internal address signal iat<k>.
The transferred external address signal eat<k> or internal address signal iat<k> is changed from low to high in level or vice versa and constantly maintained by the first inverter INV1 and second inverter INV2 of the latch 20, and then amplified and outputted as an address signal at_row<k> by the output driver 30.
However, since this latch operation is performed with respect to all address signals, the number of address signal level transitions increases in the latch 20 as the number of address signals and the speed of a DRAM increase. The increased number of address signal level transitions leads to an increase in the number of events of power consumption resulting from the formation of a direct current path between a supply voltage terminal and a ground voltage terminal of the latch inverter, or the second inverter INV2, during the level transition and, in turn, an increase in power consumption.